RTL Design Engineer

We are looking for an experienced RTL Design Engineer to define, design, and integrate RTL for a 5G/6G baseband processing subsystem. The subsystem consists of DSP cores, hardware accelerators, DMA engines, and on-chip interconnects, and is delivered as multiple hardened macros.

Core Skills

RTL Design

• Strong Verilog / VHDL for synthesizable, high-throughput datapath and control logic.
• Ability to take a block from microarchitecture spec to clean RTL.

Subsystem Integration

• Integrating DSP cores, accelerators, DMA, memories and AXI/AHB/APB fabrics.
• Address maps, interrupts, reset and clock domains.

Baseband / DSP Background

• Familiarity with the 5G NR PHY chain (FFT/iFFT, channel estimation, MIMO, LDPC/Polar, beamforming).
• Understanding of fixed-point arithmetic and how the algorithm becomes hardware.

PPA Awareness

• Design for area, timing and power.
• Memory partitioning, pipelining, clock gating and multi-power-domain design (UPF).
• Ability to read synthesis and PnR reports and work closely with the backend team on floorplan and timing closure.

Quality Checks

• Lint, CDC/RDC, synthesis and STA constraints (SDC), and LEC.
• Support verification teams with test planning, coverage closure and debug.

Tools and Flow

• Synopsys or Cadence front-end tools.
• Scripting in Python, Tcl or Perl.
• Version control with Git or similar.

Nice to Have

• Experience with licensable IP or customer-facing subsystem delivery (integration guides, customer support).
• Low-power architecture.
• DFT awareness (scan, MBIST).
• Advanced-node (≤7nm) background.
• Hands-on work integrating licensable DSP cores.

Referral

We are always searching for new talents and welcome your recommendations.

Have someone on your mind? Send their CV to us.

For a successful hire for this position, you will receive a 500 USD Gross bonus.