Physical Design Engineer

location_onSan Jose, Santa Clara Countyschedule13 hours ago
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Job description

Job Responsibilities

Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners. Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence. Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.

Skills mentioned


Cybersecurity, Data Analytics
San Jose, Santa Clara County

eInfochips, an Arrow company, is a global leader in product engineering and semiconductor design, delivering over 500 products and 40 million deployments worldwide. They specialize in silicon engineering (ASIC/FPGA design, verification, physical design), embedded systems, and software engineering, providing end‑to‑end services from cloud enablement and IoT solutions to QA and test automation. The company offers a rich portfolio of IPs—including IoT gateway frameworks, video management, and reusable camera modules—supporting rapid prototyping and lifecycle management across multiple verticals. eInfochips differentiates itself through a culture of innovation, a deep focus on quality and talent, and a commitment to delivering secure, scalable solutions on leading cloud platforms such as AWS and Azure.

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